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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4720B HEF4720V LSI 256-bit, 1-bit per word random access memories Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories DESCRIPTION The HEF4720B and HEF4720V are 256-bit, 1-bit per word random access memories with 3-state outputs. The memories are fully decoded and completely static. Recommended supply voltage range for HEF4720B is 3 to 15 V and for HEF4720V is 4,5 to 12,5 V; minimum stand-by voltage for both types is 3 V. The use of LOCMOS gives the added advantage of very low stand-by power. The circuits can be directly interfaced with standard bipolar devices (TTL) without using special HEF4720B HEF4720V interface circuits. The memory operates from a single power supply. The separate chip select input (CS) allows simple memory expansion when the outputs are wire-O Red. If CS is HIGH, the outputs are floating and no new information can be written into the memory. The signal at O has the same polarity as the data input D, while the signal at O is the complement of the signal at O. The write control W must be HIGH for writing into the memory. Fig.1 Functional diagram. HEF4720BP; HEF4720VP(N): 16-lead DIL; plastic (SOT38-1) HEF4720BD; HEF4720VD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4720BT; HEF4720VT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA See Family Specifications. January 1995 2 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories IDD LIMITS See below. FUNCTION TABLE CS L L H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial Z = high impedance OFF-state W H L X O data written into memory data written into memory Z O complement of data written into memory complement of data written into memory Z inhibit read MODE write PINNING CS W D A0 to A7 O O HEF4720B HEF4720V chip select input (active LOW) write enable input data input address inputs 3-state output (active HIGH) 3-state output (active LOW) SUPPLY VOLTAGE RATING HEF4720B HEF4720V -0,5 to 18 -0,5 to 18 RECOMMENDED OPERATING 3,0 to 15,0 4,5 to 12,5 STAND-BY MIN. 3 3 V V The values given at VDD = 15 V in the following DC and AC characteristics, are not applicable to the HEF4720V, because of its lower supply voltage range. DC CHARACTERISTICS VSS = 0 V Tamb (C) VDD V Output current LOW Quiescent device current Input leakage current HEF4720V HEF4720B 10 15 IIN 0,3 0,3 0,3 0,3 1 A 1 A 4,75 10 15 5 10 15 IDD VOL V 0,4 0,5 1,5 IOL SYMBOL -40 MIN. 2,4 4,8 10,0 25 50 100 +25 +85 MIN. 1,6 3,2 7,5 25 50 100 MAX. mA mA mA 200 A 400 A 800 A MAX. MIN. MAX. 2 4 10 January 1995 3 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories AC CHARACTERISTICS VDD V 5 Output capacitance 10 15 CO SYMBOL MIN. TYP. 5 5 5 MAX. pF pF pF HEF4720B HEF4720V A.C. CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Read cycle 5 Read access time Chip select to output time 10 15 5 10 15 5 Address hold time Output hold time with respect to address input Output hold time with respect to chip select input Output floating time with respect to chip select input Read cycle time Output transition times LOW to HIGH HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 tTHL tTLH tRC tCOF 0 0 0 580 220 160 60 30 20 40 22 15 120 60 40 80 40 30 tCOH tVAL1 tOA 0 0 0 60 20 15 170 50 40 130 70 60 tCO tACC 320 130 100 580 220 160 180 70 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 14 ns + (0,52 ns/pF) CL 11 ns + (0,22 ns/pF) CL 7 ns + (0,16 ns/pF) CL 142 ns + (0,55 ns/pF) CL 38 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 292 ns + (0,55 ns/pF) CL 118 ns + (0,23 ns/pF) CL 92 ns + (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 4 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Write cycle 5 Write cycle time Address to write set-up time 10 15 5 10 15 5 Write pulse width 10 15 5 Write recovery time 10 15 5 Data set-up time 10 15 5 Data hold time Chip select set-up time with respect to write pulse Chip select hold time with respect to write pulse Chip select lead time over write pulse to prevent writing 10 15 5 10 15 5 10 15 5 10 15 tCSL tCSH tCSW tDH tDW tWR tWP tAW tWC 580 220 160 110 50 50 370 130 80 100 40 30 250 100 80 100 30 20 370 130 80 0 0 0 0 0 0 ns ns ns ns ns ns 10 000 ns 10 000 ns 10 000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. HEF4720B HEF4720V January 1995 5 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V VDD V Read-modify-write cycle Read enable hold time Output hold time with respect to write pulse Read-modify-write cycle time 5 10 15 5 10 15 5 10 15 SYMBOL MIN. TYP. MAX. 0 tRH 0 0 60 tVAL2 20 15 1050 tRWC 390 270 ns ns ns ns ns ns ns ns ns Fig.3 Read cycle timing diagram. January 1995 6 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V Fig.4 Write cycle timing diagram. January 1995 7 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 8 Fig.5 Read-modify-write cycle timing diagram. Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories APPLICATION INFORMATION Extension of memory capacity The memory capacity of the HEF4720B; V is 256 bits (or 256 words of 1 bit). The capacity of a system can be extended in various ways by the connection of further HEF4720B; V ICs. HEF4720B HEF4720V Extending the word length By connecting a number of HEF4720B; V ICs as shown in Fig.6, the word length (i.e. bits per word) is multiplied by that number. That is, each device stores 1 bit per word but the total number of words remains 256. For example, if four devices are used in this way, 256 four-binary-bit words can be stored. Extending the number of words If a number of HEF4720B; V ICs are connected as shown in Fig.7, the words available are multiplied by that number, but the word length remains 1 bit. Notice that in this case additional addresses are used in conjunction with the CS input. In the case shown in Fig.7 (4 x HEF4720B; V in parallel), the addresses and data inputs are loaded with four inputs (= 20 pF), the CS inputs are loaded with one input each. Extending both the word length and number of words Figure 8 shows how a combination of the extensions described above can be used to obtain both greater word length and additional words. It is clear that the capacitive load of the driving circuits puts a limit to the free choice of the interface. In Fig.8, each address is loaded with 16 inputs, i.e. 16 x 5 = 80 pF: each CS inverter is loaded with 8 inputs, i.e. 8 x 5 = 40 pF. The data inverters in this case are loaded with only two inputs each. January 1995 9 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V Fig.6 Using extra HEF4720B; V ICs to extend the word length. January 1995 10 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 11 Fig.7 Using extra HEF4720B; V ICs to obtain more words. Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V Fig.8 Using extra HEF4720B; V ICs to obtain more words and greater word length. January 1995 12 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories Memory retention It is sometimes necessary to ensure that the information stored in the memory cannot be erased inadvertently. This can be arranged by adding detection circuits, by measures in the timing, and by the addition of a battery. With the HEF4720B; V, memory retention is very easily obtained because its current drain in the stand-by condition is almost zero. The wide supply voltage range makes it possible to keep the memory active by means of a simple battery, thereby preventing information loss. In designing the memory retention circuits, two aspects should be kept in mind. The memory retention will not function in an optimum way if the battery voltage is low or if the voltage transitions at the address input are too slow. The first of these is usually the result of using too simple a battery back-up circuit, e.g. a battery charged via a diode from the TTL supply voltage. In this case, the LOCMOS supply voltage falls below the safe operating voltage. Special arrangements should be made to overcome this. Slow address transitions (the second cause of memory loss) are due to a long RC-time in the power system. When the power is switched on or off, the 5 V line changes between 0 and 5 V in milliseconds to seconds so producing a correspondingly long transition time in the various logic outputs. This creates problems in the proper operation of the HEF4720B; V, with loss of memory as a possible result. This can be prevented by ensuring that input rise and fall times do not exceed 10 s. HEF4720B HEF4720V Three possibilities for controlling the rise and fall times at the HEF4720B; V interface are given here: 1. LOCMOS gates can be connected between the address latch and the HEF4720B; V (Fig.9). In the event of a low voltage, or mains supply failure, the gates can be blocked by a signal from the memory retention logic thus isolating the HEF4720B; V from the address and CS inputs. 2. The interface power supply can be separated from the TTL power supply by means of a low-value resistor (Fig.10); a thyristor is connected from the interface power supply to earth. The system is arranged so that, upon switching off or failure of the interface supply, the thyristor turns on thus ensuring a rapid fall of the supply voltage. 3. The best solution is to select the interface circuits from the LOCMOS family and to feed all these circuits from the battery (Fig.11). These stages then remain active when the TTL 5 V supply fails. The interface circuits are mostly only active on a clock pulse, have the possibility of being inactive on a gate level, or can be forced into one position. January 1995 13 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V (1) These devices have a battery supply. (2) Alternative connection. Fig.9 Use of battery-operated LOCMOS gates to isolate the memory in case of power supply failure. Devices marked (1) are connected to the battery. The HEF4011B can sink about 0,7 mA: if the load is greater than this, only the memory should be connected, other loads being connected to the address latch as shown by the dashed-line connections. January 1995 14 Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V (1) Leads should be so arranged to prevent cross-talk; thyristor connections must be short. (2) Slope > 500 mV/s in the vicinity of the threshold. Fig.10 Using a thyristor to ensure a rapid fall of interface supply at switch-off or supply failure. January 1995 15 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 16 Fig.11 Preferred solution for memory retention; all interface circuits are battery-fed LOCMOS. Note that maximum sink current of the HEF4042B is about 1,5 mA. Philips Semiconductors Product specification 256-bit, 1-bit per word random access memories HEF4720B HEF4720V |
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